I think you guys are misreading this a little bit. It's a business decision primarily, and a technical one secondarily, but I love the technical part so mostly I'll focus on that.
Apple bought PA Semi (Dan Dobberpuhl's company) many years ago - this is the team that is implementing their ARM cores. Apple has an ARM architectural license, dating from the earliest days (I believe going back to Newton), so free reign to do a lot of things. They are trying to balance the need for x86 ABI compatibility with the cost of being attached to Intel for a key component - this is the basic business decision. Apple has staffed that ex-PA team to high heavens - I believe they had 150-200 people at the beginning and have heard rumors of 1000+ now. So they can probably get quite a lot done, but they are still small compared to the teams at Intel doing this stuff.
Intel (with x86) is biased micro-architecturally to higher performance, and ARM to lower power, but there is nothing at the ISA level that forces that, it's just what they make. In fact, in energy (not power) terms, you
can see (fig 10) that energy for the x86 is not way out of line with ARM's A15 - depends on workload but in some cases x86 is more efficient. You can also see in that link at fig 11 that the power-MIPS (BIPS) tradeoffs are really just a line that different micro-architectures sit on at different points. Put another way, I think you can make a big high-power ARM core, but because the ARM licensees are micro-architecturally biased to low-energy, no one does it yet - Apple might be able to, but there's a lot to figure out here. Since that link is an ARM-centric blog, I need to think a little more about where they (ARM) might have inserted bias, but as far as I know it is derived from a pretty fundamental
paper from Wisconsin published ~5 years ago. It would also be nice to see those results on A57 or newer, since A15 is rather long in the tooth, but I bet it holds up.
I liked the comments from
@jimv - but what I have read is that Intel's 10nm might be competitive with GF (i.e. Samsung's) 7nm in terms of actual achieved
density - and maybe better on some process performance metrics. So even if INTC has bungled some things, they are pretty damn good at this process stuff, maybe good enough. I need to dig more on TSMC's equivalent in that node.
Last comment, because I have to as a security dude - I think that barring some major miracle, out-of-order execution + superscalar architectures that have dominated the last 20-25 years are well and truly fucked in the face of
Spectre - the Meltdown stuff can be basically patched, but I have serious doubts about Spectre. The memory hierarchy we are used to might have to substantially change (can't have shared L2/L3 caches anymore) or maybe have to migrate to massive core-count superscalar but non-speculative ultra-high-clock-rate devices, which poses its own issues in terms of power/energy, or even feasibility.
I need to find a Sons of Yale Patt board to get more gossip on this stuff - it's fascinating times right now.
